plls

The research of this project is concentrated on PLLs phase noise. It aimed at discovery some special difficulty in implementing phase-locked system.

本文主要研究了锁相环的相位噪声问题，研究目的在于揭示锁相系统设计过程面临的一些特殊问题。

But PLLs design process involves much theory and application base, such as signal and system, integrated electronics, layout, semiconductor technology, measurement etc.

但是锁相环的设计过程，涉及到信号与系统、集成电子学、版图、半导体工艺和测试等方面，难度比较大。

These limits place tough constraints upon digital interface design, and it is recommended that interface receiver PLLs have closed-loop cutoff frequencies as low as possible.

这些限制的地方后，数字接口的设计硬约束，并建议该接口的接收器PLL具有闭环截止频率尽可能低。